The significance of defects in memory systems is such that considerable effort has been invested to provide repairable arrays using redundant memory array rows, redundant memory array columns, or both. These redundant/spare memory lines (i.e., rows or columns) are not activated for use in the memory array unless post-manufacture testing indicates that a defect exists in the main memory array structure. When a fault is detected in the main memory array structure, a redundant memory array row or column, is substituted for the row or column containing the fault. The final result is that the memory array is fully functional and the fault in the main array is avoided by activating a redundant line to substitute for the faulty memory line (i.e., either row or column). The final yield of a memory system incorporating such redundant structures is greatly improved relative to a memory system in which a single failure results in the whole memory system being scrapped.
Known redundant structures fall into one of two broad types of redundant architectures: (1) cache/tag architectures; and (2) fuse-based architectures.
In a cache/tag based architecture, a small array of memory lines and corresponding address tags are placed on the same chip as the memory array. When defects are discovered during testing, individual cache lines are mapped, via the tags, to replace the faulty memory lines. The mapping is accomplished by storing the address or "tag" of the defective line(s) into the tag associated with one or more of the cached replacement line(s). Subsequent accesses of the faulty main array address use the memory cells in the cached replacement line. Cache/tag architectures are generally complex structures, require significant space to implement, and consume excessive power resulting in reliability issues. In addition, a parallel access to the defective line in main memory occurs, resulting in the dissipation of excess current, especially when the failure mechanism of the line is high current failure related.
One example of such a prior art device having memory built in self repair (MBISR) is a content addressable memory (CAM) used to repair defective rows within the memory array. In this prior art device if an address to the memory array matches an address stored in the CAM, then data is supplied from the CAM instead of the defective row of memory. However in this prior art device the sense amplifier for the defective row in the array continues to function even though the CAM is supplying the data. This dual access can affect reliability by leading to high current drain and electromigration problems. In addition this prior art device degrades the speed at which the array can be accessed because a MUX is required to select between the array and the CAM.
In a fuse-based architecture, a replacement row is selected by blowing a fuse associated with a defective memory row. Once the fuse is blown, the defective address is remapped either: (1) directly to a redundant memory row; or (2) to the next functional memory row in the memory array. In the second case, every other subsequent memory row (which is not defective) is also remapped to the next subsequent memory. This style of redundancy is also known as a "push-down" architecture since a fault is corrected by incrementing all memory row pointers to point to a subsequent (row+1). The last row in the memory array now points to a redundant row in the memory array.
This push down feature is conventionally accomplished using laser hardware to replace, by cutting and connecting, faulty bits with redundant rows or columns. Finding the exact physical location on the silicon wafer or die requires a program to calculation and store the location so that the laser machine can cut and mend the faulty locations with the redundant location. This procedure requires purchasing the laser hardware and substantial test time, effectively increasing overhead.
One prior art device using a push down feature uses built in self repair to repair defective rows within the memory array. However, in this prior art device, once a first defective row is patched, only 50% of any subsequent defective rows can be repaired using a second redundant row. Specifically in this prior art device if defects occur in 2 odd rows or 2 even rows they cannot both be repaired. Thus this prior art device has limited reparability.
Both fuse-based strategies outlined above require a process that supports fuse formation. These processes can be more complex than typical integrated circuit (IC) processes. The fuses are typically formed in a lower conductive layer of material (such as a second level of polysilicon). Therefore, complex etch processing is used to etch through passivation, inter-level dielectrics, nitride layers, etch and polish stop layer, and the like to expose the fuse to laser operations. These etches to form a fuse opening are complex and may adversely affect yield. Further, the process of blowing fuses requires an additional assembly/laser step after test. The process of blowing the fuse with a laser vaporizes the fuse leaving particle residue on the die surface and within fuse openings. This residue is sometimes conductive resulting in electrical short circuits or leakage paths. Also, fused repair must be performed before packaging the die, must be performed in the factory, and can never be undone or used later in the life of the memory system. Therefore, once a fuse is blown, it cannot be "unblown". In addition, once the IC is packaged, the laser repair operation cannot be performed through the IC package and subsequent end-user repair is impossible which adversely affects IC lifetime.
Therefore, a need exists for a memory repair redundancy system which is more versatile and safe than fuse-based repair and more area-efficient and less-complex than cache-based repair.